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CY62146CV30 MoBLTM
256K x 16 Static RAM
Features
* High speed: -- 55 ns and 70 ns availability * Voltage range: -- CY62146CV30: 2.7V - 3.3V * Pin compatible with CY62146V * Ultra-low active power -- Typical active current: 1.5 mA @ f = 1 MHz * * * * -- Typical active current: 7 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by 99% when deselected (CE HIGH). The input/output pins (I/O0 - I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 - I/O7), is written into the location specified on the address pins (A0 - A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 - I/O15) is written into the location specified on the address pins (A0 - A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 - I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of Read and Write modes. The CY62146CV30 is available in 48-ball FBGA packaging.
Functional Description
The CY62146CV30 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBLTM) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
256K x 16 RAM Array 2048 x 2048
SENSE AMPS
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER BHE WE CE OE BLE
Cypress Semiconductor Corporation Document #: 38-05203 Rev. **
*
3901 North First Street
A14 A15 A16 A17
A11
A12
A13
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San Jose
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CA 95134 * 408-943-2600 Revised December 17, 2001
CY62146CV30 MoBLTM
Pin Configuration[1,2]
FBGA (Top View) 4 5 3 A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC
2 OE
6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H
BHE I/O10 I/O11
I/O12 DNU I/O13 NC A8 A14 A12 A9
Product Portfolio
Power Dissipation (Industrial) Product VCC(min.) CY62146CV30 2.7V VCC Range VCC(typ.)[3] VCC(max.) 3.0V 3.3V 55 ns 70 ns Speed Operating, ICC f = 1 MHz Typ.[3] 1.5 mA 1.5 mA Max. 3 mA 3 mA f = fmax Typ.[3] 7 mA Max. 15 mA 12 mA 25 mA Standby (ISB2) Typ.[3] 7 A Max. 15 A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ...-0.5V to Vccmax + 0.5V DC Voltage Applied to Outputs in High-Z State[4] ....................................-0.5V to VCC + 0.5V
DC Input Voltage[4].................................... -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current ................................................... > 200 mA
Operating Range
Device CY62146CV30 Range Industrial Ambient Temperature VCC
-40C to +85C 2.7V to 3.3V
Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or VSS to ensure proper application. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. 4. VIL(min.) = -2.0V for pulse durations less than 20 ns.
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CY62146CV30 MoBLTM
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ -55 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- CMOS Inputs Automatic CE Power-Down Current-- CMOS Inputs GND < VO < VCC, Output Disabled f = fMAX = 1/tRC
f = 1 MHz
-70 Max. 0.4 Min. 2.4 0.4 1.8 -0.3 -1 -1 7 1.5 VCC + 0.3V 0.8 +1 +1 15 3 mA VCC + 0.3V 0.8 +1 +1 Typ.[3] Max. Unit V V V V A A
Test Conditions IOH = -1.0 mA IOL = 2.1mA VCC = 2.7V VCC = 2.7V
Min. 2.4 2.2 -0.3 -1 -1
Typ.
[3]
ICC
VCC = 3.3V IOUT = 0 mA CMOS Levels
12 1.5
25 3
ISB1
CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f=0 (OE,WE,BHE and BLE) CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, Vcc=3.3V
7
15
7
15
A
ISB2
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF
Thermal Resistance
Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5]
Note: 5. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, four-layer printed circuit board
Symbol JA JC
BGA 55 16
Units C/W C/W
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CY62146CV30 MoBLTM
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH R2
VCC Typ 10% GND Rise TIme: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns
Parameters R1 R2 RTH VTH
3.0V 1.105 1.550 0.645 1.75V
Unit KOhms KOhms KOhms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[5] tR[6] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC= 1.5V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 3 Typ.[3] Max. Vccmax 10 Unit V A ns ns
Note: 6. Full device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100s or stable at VCC(min.) >100 s.
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CY62146CV30 MoBLTM
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Switching Characteristics Over the Operating Range[7]
-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[9] tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[11]
-70 Max Min 70 55 70 10 55 25 70 35 5 20 25 10 20 25 0 55 25 70 35 5 20 25 70 60 60 0 0 50 60 30 0 20 25 5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[8] OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z
[8,10] [8] [8, 10]
Min 55 10
5 10 0
CE LOW to Power-Up CE HIGH to Power-Down BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z BHE / BLE HIGH to High Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BHE / BLE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[8, 10]
5
55 45 45 0 0 45 50 25 0 5
WE HIGH to Low Z[8]
Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. If both byte enables are toggled together, this value is 10 ns. 10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 11. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write.
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CY62146CV30 MoBLTM
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
[12, 13]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATAIN VALID
Read Cycle 2 (OE Controlled)
[13, 14]
ADDRESS
CE tACE OE
tRC tPD tHZCE
BHE/BLE
ttLZOE LZOE
tDOE
tHZOE
tHZBE
tDBE
tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
Notes: 12. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
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CY62146CV30 MoBLTM
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)
[11, 15, 16]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 17 tHZOE
[11, 15, 16]
tHD
DATAIN VALID
Write Cycle 2 (CE Controlled)
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD
Notes: 15. Data I/O is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied.
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CY62146CV30 MoBLTM
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)
[16]
tWC ADDRESS tSCE CE
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATAI/O NOTE 17 tHZWE DATAIN VALID
tHD
tLZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)
[16]
tWC ADDRESS
CE tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 17 DATAIN VALID tHD tBW tHA
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CY62146CV30 MoBLTM
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.) Operating Current vs. Supply Voltage 14.0 12.0 10.0 MoBL2 8.0 ICC (mA) 6.0 4.0 2.0 (f = 1 MHz) 0.0 2.7 3.0 3.3 0 2.7 3.0 3.3 ISB (mA) (f = fmax, 70 ns) (f = fmax, 55 ns) 12.0 10.0 MoBL2 8.0 6.0 4.0 2.0 TAA (ns) 60 50 40 30 20 10 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V) Standby Current vs. Supply Voltage Access Time vs. Supply Voltage MoBL2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Truth Table
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (I/OO - I/O15) Data Out (I/OO - I/O7); I/O8 - I/O15 in High Z Data Out (I/O8 - I/O15); I/O0 - I/O7 in High Z High Z High Z High Z Data In (I/OO - I/O15) Data In (I/OO - I/O7); I/O8 - I/O15 in High Z Data In (I/O8 - I/O15); I/O0 - I/O7 in High Z Mode Deselect/Power-Down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
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CY62146CV30 MoBLTM
Ordering Information
Speed (ns) 70 55 Ordering Code CY62146CV30LL-70BAI CY62146CV30LL-70BVI CY62146CV30LL-55BAI CY62146CV30LL-55BVI Package Name BA48B BV48A BA48B BV48A Package Type 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range 48-ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) Industrial
Package Diagrams
48-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA48B
51-85106-*C
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CY62146CV30 MoBLTM
Package Diagrams (continued)
48-ball (6.0 mm x 8.0 mm x 1.0 mm) Fine Pitch BGA BV48A
51-85150-**
MoBL, MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62146CV30 MoBLTM
Document Title: CY62146CV30 MoBLTM 256K x 16 STATIC RAM Document Number: 38-05203 REV. ** ECN NO. 112395 Issue Date 01/18/02 Orig. of Change GAV New Data Sheet Description of Change
Document #: 38-05203 Rev. **
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